1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having high packaging reliability.
Particularly, the invention relates to a semiconductor integrated circuit device provided with the facedown bonding bumps having an electrical connection capability that are provided at a terminal section on the surface of a semiconductor substrate and which has electrically-non-connected dummy bumps.
2. Description of the Related Art
Performance enhancement of electronic devices has recently been pursued, and a semiconductor integrated circuit packaged in the devices is required to have high performance and complicated features. Means for enabling high-density packaging is demanded particularly for a semiconductor integrated circuit device to be provided in small equipment, such as a portable data terminal or portable cellular phone and so on.
For theses reasons, a semiconductor integrated circuit device has been conventionally packaged as a chip without performing plastic sealing. Therefore, a method has been adopted for providing projections, such as known for bumps, on the terminals of a chip and mounting the chip to a substrate by a flip chip bonding method. Specifically, when a semiconductor integrated circuit device is packaged, facedown bonding is adopted for placing a chip opposite an object of connection, such as a substrate, and pressing the chip directly on the substrate using anisotropic conductive particles (ACP) or a conductive material.
In this case, since the back side of the chip is ground due to a need for slimming down a chip, the chip comes to be warped or susceptible to variations in its thickness, and furthermore the horizontal positions of the bumps formed on the surface of the chip are also displaced (see FIG. 7(a))
In such an occasion, one of the four corners of the chip often comes into contact with the substrate at first prior to the rests of the corners doing in the facedown mounting because of fluctuations in the height of bumps or the insufficient precision of a bonding machine used for bonding a chip on the mounting substrate (see FIG. 7(b)).
Consequently, when the chip is mounted, bumps located around the four corners of the chip are subjected to heavier load stress than that imposed on bumps disposed around the center of the peripheral edges of the chip. For the purpose of protecting the bumps or an electrical circuit on the chip by eliminating an unbalance in load stress, electrically-non-contact dummy bumps have been conventionally provided such as described in JP-A-8-46313 or JP-UM-T-4-94732.
It is also disadvantageous to adopt the dummy bumps that are disclosed in JP-A-8-46313 from the reason such that the dummy bumps are arranged to be abutted to the edges of the chip, whereby unfavorable particles might be produced in case of dicing the wafer into the chips.
Furthermore, JP-A-7-263488 discloses the dummy bumps. However, the dummy bumps are not used for the purpose of the facedown bonding, and besides, there is no idea of solving the problems such as the chip being warped or susceptible to variations in its thickness or subjected to the heavier load stress.
In recent years, because of an improvement in performance of an LSI; particularly, due to colorization of an LCD driver or a tendency of the larger size of a screen, the numbers of the terminals to be used are increased, and a highly-integrated semiconductor process is required. In such an occasion, downsize of a chip area cannot be achieved unless intervals between bumps are made narrower than they have been made before. In recognition of this requirement, the area of each bump also comes to be smaller, which ended up increasing the number of dummy bumps to be disposed at each of the corners of one chip.
The related-art semiconductor integrated circuit device is limited in narrowing the interval between the bumps, because of a particle size (3 μm to 5 μm) of the anisotropic conductive particles (ACP), which shall ensure at least a distance from 10 μm to 15 μm between the bumps.
In contrast, the areas of the individual bumps are required to be substantially the same in size with each other from a need of electrically connecting the chip with the substrate in use of the ACP. As a result, as shown in FIG. 8, each of the respective bumps in case of narrowing the interval between the bumps might become a narrow shape. For these reasons, as the numbers of the dummy bumps increase the so-called invalid area (hatched in FIG. 8), a space residing between the bumps, becomes larger in the ratio of the bump area. Accordingly, an increase in the number of dummy bumps merely results in increase of the area where the dummy bumps are disposed in relation to the total area of the bumps, which becomes a limitation on downsizing of a chip.
Reflecting these requirements, in the related art, the following has been adopted. FIG. 1 is a view showing the entirety of a chip of a semiconductor integrated circuit device to be used for facedown bonding of the related art. The semiconductor integrated circuit device chip 1 has facedown bonding bumps 6 arranged so as to surround unillustrated internal circuit. In the embodiment, bumps are arranged along four sides of a chip 1 of the semiconductor integrated circuit device surrounding the internal circuit. In an alternative configuration, no bumps 6 are provided along one or two specific edges, and a circuit or wiring is provided instead of the bumps.
FIGS. 2 is an enlarged view showing a chip corner section 5 enclosed by broken edges in FIG. 1 as a representative of four corners of the semiconductor integrated circuit device chip 1. The drawings will be described herein below.
FIG. 2 is a view showing the layout of related-art bumps. There are provided circuit connection bumps 3 connected to an unillustrated internal circuit, and two dummy bumps 2 which are placed for each edge, between the corner section of the chip 1 of the semiconductor integrated circuit device and the bumps 3. There can be obtained a load capacity effect of an area corresponding to the area occupied by a total of four circuit connection bumps 3. An inside of the area enclosed by broken line corresponds to the area on the chip 1 of the semiconductor integrated circuit device ensured for dummy bumps.
However, this related art is still not sufficient for overcoming the above-mentioned problems from the aspects of the recent improvement functionalities of LSI technologies or highly advanced semiconductor integration processes.